The present invention relates to an MCP (Multi-Chip Package) semiconductor disk device capable of expanding memory and to a semiconductor device with provisions to facilitate testing a plurality of chips accommodated in an MCP (Multi-Chip Package).
As demands are growing for higher integration density of semiconductor devices mounted on a printed circuit board, the packages of semiconductor devices are getting smaller. In recent years, a variety of kinds of CSPs (chip size packages), a general reference to packages equal to or slightly larger than the chip size, have been developed. (The CSP package type is classified as a derivative of the existing packages.) They are making large contributions to reducing size and weight of portable terminals.
At the same time, since the speed at which the memory capacity required by the system devices increases is higher than the speed at which the memory integration improves, a three-dimensional mounting of a memory has been proposed as a means to increase the memory capacity while minimizing an increase in the memory mounting area. The applicant of this invention developed a technology of DDP (Double Density Package) in which an LOC (Lead On Chip) structure is formed in layers to double the memory capacity of a package with the same external size as the 1-mm-thick surface mount package TSOP (see JP-A-11-163255, laid open on Jun. 18, 1999, corresponding to U.S. patent application Ser. No. 09/161,725 filed on Sep. 29, 1998). This publication discloses a 128 MDRAM-DDP, in which LOC structure (64 MDRAM) lead frames are stacked in layers and sealed with a mold, with the leads bonded.
Unlike a conventional magnetic disk device, a semiconductor disk device using a flash memory has no mechanical moving parts, and thus is unlikely to have erroneous operations and failures due to physical impacts. It has the advantages of being smaller in device size and able to make a faster read/write access to data than in the conventional magnetic disk device. The semiconductor disk device has conventionally been realized as a memory board or memory card having a plurality of flash memories and a controller that controls the flash memories. In this case, the plurality of flash memories are realized as discrete LSIs and the controller is also realized as one LSI.
To deal with the aforementioned problem that a large number of parts in the semiconductor disk device makes the size reduction difficult, JP-A-6-250799, laid open on Sep. 9, 1994, discloses a semiconductor disk device in which a flash memory unit, an interface with external devices, and a controller unit are integrated in a single LSI. The semiconductor disk device of a one-semiconductor-chip configuration has an expansion memory interface which, when the user wishes to expand the flash memory built into the chip, allows the storage capacity of the semiconductor disk device to be increased, as required, by the user externally connecting a flash memory one chip at a time.
JP-A-11-86546, laid open on Mar. 30, 1999, discloses a technology whereby a logic chip and a memory chip, fabricated separately, are mounted parallelly and sealed in one package. Further, JP-A-11-19370 (corresponding to U.S. patent application Ser. No. 09/450,676, filed on Nov. 30, 1999) shows an example structure of MCP.
The inventors of this invention studied a semiconductor disk device suited for incorporation into various portable information terminals (palm size PC, handy terminal, etc.) and digital cameras as main products to which the invention can be applied. The specifications require the semiconductor disk device to have the smallest possible mounting area, weight and power consumption. A controller is available in a variety of kinds for various applications. For security reasons, the controller is expected to have its specification updated frequently, so that it is important to shorten the development period of new package products to reduce costxe2x80x94the common priority among the commercial products.
When a semiconductor disk device disclosed in JP-A-6-250799 is to be manufactured in a single semiconductor chip configuration, i.e., in the form of a system LSI, the following problems may arise: (1) there is a need to develop a new process, which in turn increases the number of processes, leading to an increase in cost; (2) when all the constitutional units are manufactured by the same process, the performances of the individual units may become worse than when the individual units are fabricated in the dedicated processes; (3) redesigning the entire chip as a result of changes in the specifications of the controller unit is not advantageous in terms of reducing the development cost and shortening the development TAT; and (4) because the constitutional units are arranged two-dimensionally, the size becomes large for a single chip.
In the LSI incorporated into a single package by arranging a plurality of chips parallelly as described in JP-A-11-86546, the reduction in the mounting area remains small to an extent that the mounting area is not smaller than the sum of the areas of the individual chips.
(1) A first object of the present invention is to propose a package configuration for the semiconductor disk device, which has a small mounting area to facilitate its incorporation into small portable information terminals, and which can cope quickly with type changes of the controller due to specification changes, reduce the development TAT (Turn Around Time: time spent from the material processing to the delivery of a product; or number of days from the start of development to the completion of development) and keep the development cost low.
Further, in a proposal to construct a semiconductor disk device in the MCP configuration, the inventors of this invention studied the problems experienced when conducting tests on a product incorporating a memory chip and a controller chip in a single package. The existing memory and controller (logic) are individually packaged and subjected to tests individually before being mounted on the printed circuit board. When combining two chips and forming them as a single package product, it is natural to conceive also bringing into the package the xe2x80x9cwiringxe2x80x9d that is on the printed circuit board between the memory and the controller. This, however, poses a problem in the testing that is conducted before shipping of the product. When the existing memory and controller are tested as individual single packages, the memory is tested by a memory tester and the controller is tested by a logic tester. These existing test environments, however, cannot be used under the same conditions as in the conventional tests if the memory and the controller are incorporated into one package and internally interconnected as described above. When for example the memory is tested by the memory tester, the influence (leakage current) due to internally connecting the controller cannot be precluded entirely, so that the identical test cannot be conducted under the conventional memory testing environment. The same can be said of the testing of the controller. That is, even if the influences of the internal connection is reduced as much as possible and an analysis considering these influences is performed, the equality of the test is expected to deteriorate.
Further, the memory tester and the logic tester have different characteristics. As the memory capacity increases, the test time also increases. To deal with this situation the memory tester enhances the test productivity by testing a large number of memories simultaneously. As for the logic tester, on the other hand, although it uses many signal terminals for applying a very large test pattern to the LSI being tested, the test time is generally about two orders of magnitude smaller than the memory test time. Because of this characteristic, the logic tester enhances the test productivity by increasing the rate at which the LSIs are mounted and tested. If a mixed tester having both of these test functions with different characteristics is developed, the MCP packages mounted on the mixed tester may be able to be subjected to both of these test functions. However, there is a drawback that until the memory test is completed after the logic test has been finished, the logic test terminals become idle without being utilized, eventually degrading the test productivity.
Hence, in view of the test productivity, i.e., efficient utilization of the expensive test system, it is considered promising to test the memory chip and the logic chip in the MCP two times individually. To realize this, it may be necessary to add to the memory tester and the test packages a function of isolating the influences due to connecting the controller and to add to the logic tester and the test packages a function of isolating the influences due to connecting the memory.
Therefore,
(2) it is the second object of this invention to propose an MCP mounting configuration which can efficiently utilize the expensive test system originally constructed to deal with individual separate chips in a conventional manner, keep low the cost and the number of processes for the development of new test environments, and shorten the product development TAT.
(3) Further, it is checked whether the solution described above (2) that considers the efficiency of the development of test environment can be applied generally to a wide range of MCPs if the types of chips to be combined, the functions to be incorporated, and the package configuration should change.
(4) Further, it is also checked whether the present invention can similarly be applied to the system LSIs considering the problems accompanying the development of the test environment for a plurality of LSI cores.
When the mounting configurations suited for the semiconductor disk device for incorporation into a variety of portable information terminals and digital cameras are evaluated in terms of (1) small mounting area and (2) low manufacturing cost, if the chip area is 40 mm2 or greater, it is considered better to mount the memory chip and the controller chip in a stacked package (three-dimensional mounting) rather than integrating them into a one-chip system LSI (see Nikkei Microdevices, August 1999, pp. 40-45). Hence, let us consider a case where a plurality of different kinds of chips (e.g., a combination of a memory chip and a controller chip) are three-dimensionally mounted in one package. Normally, these chips have different shapes and different electrode pad arrangements and thus the package configuration in this case differs from the one in which a plurality of chips of the same shape and the same specifications are stacked as in the DDP and stack memory. Among the package types currently in wide use, the following two types may be selected considering the ability to reduce the manufacturing cost by using the existing facilities and realize a significant mounting area reduction effect.
(1) TQFP (Thin Quad Flat Package) type of four-directional lead arrangement structure in which a second semiconductor chip is stacked on a semiconductor chip of LOC (Lead On Chip) structure.
(2) Stacked chip CSP (Chip Size Package) type based on a small BGA (Ball Grid Array).
The CSP type has a better mounting area reduction effect but, in terms of the short development period for product design and the low manufacturing cost, the TQFP type using the low-cost lead frame is superior.
Among the package configurations for the semiconductor disk device suited for incorporation into various portable information terminals and digital cameras, the first proposed solution is a TQFP type which has a short development period for product design achieved by combining the existing chips and packaging them and which has the lowest manufacturing cost realized by stacking a plurality of chips on a single lead frame. The TQFP type will be disclosed in the first embodiment. As for the expansion of the memory in the semiconductor disk device, the package is provided with a memory expansion terminal. This embodiment has specifications that allow the controller to access the externally connected expansion memory in the same way as accessing the built-in memory.
Facilitating the testing of a plurality of chips incorporated in the MCP, which is the second object of the present invention, is proposed as follows.
In the embodiment 1, the controller and the flash memory in the package constituting the semiconductor disk device are basically not internally connected. The electrode pads of the controller chip and the flash memory chip are independently connected to the external terminals. The power supply or ground may be connected to a common external terminal of the two chips. When the semiconductor disk device described above is in use, it is mounted on the board and its external terminals are interconnected by wires on the board. The controller accesses the flash memory via the external terminals and the wires on the board.
With this arrangement, the flash memory and the controller in the package of this invention, when viewed from outside the package, operate independently of each other through the external terminals. Hence, by mounting the packages of this invention in the test environment that was originally developed for testing the conventional discrete chips, the memory test and logic test can be executed successively in the same way as with the individual discrete chips. With the method of this invention, reliable tests identical with the conventional ones can be performed without adding to the memory and logic test environments a function of isolating the influences of other chips.
The MCP configuration of this invention that enables independent tests is not limited to the MCP of the embodiment 1 having a combination of the flash memory and the controller (ASIC) but can be applied, with the similar effects, to any MCPs in any form of package with any number of combined chips.
As a variation of this invention, it is possible to provide a selector on the internal wires between a plurality of chips in the MCP and to supply a test mode signal from the external terminal to the selector to select between two modes, a mode in which the plurality of chips are disconnected from each other and can be independently tested from the external terminals and a mode in which the plurality of chips are internally interconnected to allow inter-chip accesses inside the package. In this case, a selector with a function of connection switching according to the mode signal is installed on the internal wires in the package or in the controller chip.
A package is provided which incorporates into a flash memory a system program conforming to the combination of a flash memory and a controller and which guarantees that the system program operates normally.